1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device in which two types of trenches having different depths are formed in a semiconductor layer.
2. Description of the Related Art
Currently, semiconductor devices such as LSIs are typically fabricated by use of silicon substrates. However, in order to further improve device characteristics, the fabrication of LSIs using silicon-on-insulator (SOI) substrates is being actively researched.
An SOI substrate has a structure in which a buried insulating layer and a silicon layer are formed in order on a supporting substrate, and is fabricated by “bond and etch-back technology”, “separation by implanted oxygen (SIMOX) technology”, or the like. In the case where a MOS transistor is formed on the SOI substrate, a trench having a depth reaching the buried insulating layer is formed around a transistor forming region, and a device isolation insulating layer is buried in the trench. Thus, the transistor forming region is electrically isolated from the surrounding region by the device isolation insulating layer and the buried insulating layer. Accordingly, the MOS transistor (hereinafter referred to as SOI MOS transistor) shows excellent device isolation characteristics.
In addition, the SOI MOS transistor is also more excellent than MOS transistors fabricated by use of silicon substrates in terms of low power consumption, a small junction capacity, high soft error resistance and latch-up resistance.
However, if the SOI MOS transistor is completely isolated by the device isolation insulating layer and the buried insulating layer as described above, the silicon layer (body) in the region which is surrounded by these insulating layers and is served as the transistor forming region is electrically floating, and the electric charge accumulated in the body cannot find any route to escape. This would vary the characteristics of a plurality of SOI MOS transistors in the order they are operated, in response to the amount of electric charge in the bodies of the each transistor, and cause a malfunction of a circuit. The phenomenon that characteristics of SOI MOS transistors vary in accordance with their operational histories in the past as described above is called history effect. For bringing out characteristics of SOI MOS transistors to the maximum, this history effect needs to be reduced.
In order to reduce the history effect, a structure called a hybrid trench structure has been proposed. In the hybrid structure, as shown in FIG. 1 of Non-patent Literature 1, a full trench and a partial trench coexist as trenches, in which device isolation insulating layers are to be buried. The full trench has a depth reaching a buried insulating layer. On the other hand, the partial trench does not reach the buried insulating layer, and a silicon layer remains under the partial trench. This makes it possible to control the electric potential of the silicon layer, which is to be a body, and to extract the electric charge of the body, through the silicon layer under the partial trench. Accordingly, the aforementioned history effect can be reduced.
The hybrid trench structure tends to be further miniaturized in the future, and need to be formed through a process compatible with a fine design rule, e.g., by photolithography in which ArF excimer laser light is used.
In Patent Literatures 1 and 2, after a partial trench is formed by use of a photoresist pattern as a mask, a full trench is formed by use of a silicon dioxide (SiO2) layer as a hard mask.    (Patent Literature 1)    Japanese Unexamined Patent Publication No. 2001-168337    (Patent Literature 2)    U.S. Pat. No. 6,498,370    (Non-patent Literature 1)    Y. Hirano et al., International electron devices meeting 2000, pp. 467–470
Incidentally, if the formation of a hard mask made of a silicon dioxide layer as in Patent Literature 1 is attempted by photolithography in which ArF excimer laser light is used, something like the following process is performed. FIGS. 1A to 1C are cross-sectional views showing steps in a manufacturing method of a semiconductor device according to a prior art. FIG. 2 is a plan view for explaining a disadvantage of the manufacturing method of the semiconductor device according to the prior art.
First, as shown in FIG. 1A, a pad oxide layer 202, a pad silicon nitride layer 203, and a hard mask 204 made of silicon dioxide are formed in this order on a silicon layer 201 of an SOI substrate. After that, a photoresist pattern 205 exposed with ArF excimer laser light is formed on the hard mask 204.
Subsequently, as shown in FIG. 1B, the layers from the hard mask 204 to the pad oxide layer 202 are sequentially etched by use of the photoresist pattern 205 as a mask, thus making the layers 202 to 204 left under the photoresist pattern 205 into a trench mask 206. Thereafter, the photoresist pattern 205 is removed.
Then, as shown in FIG. 1C, the silicon layer 201 is etched by use of the trench mask 206 as an etching mask, thus forming trenches 201a such as a full trench and a partial trench in the silicon layer 201.
However, ArF photoresist used as the photoresist pattern 205, e.g., chemically amplified positive photoresist having an alicyclic structure, has small etching selectivities to silicon dioxide and silicon nitride. This is based on the following reasons.
In general, ArF photoresist need to transmit ArF excimer laser light at a wavelength of 193 nm. Accordingly, unlike KrF photoresist, ArF photoresist cannot contain an aromatic ring, which absorbs light at wavelengths of 200 nm or shorter. Therefore, the above-described alicyclic structure is employed in ArF photoresist, but an alicyclic structure is inferior to an aromatic ring in etching resistance. Furthermore, in the case of ArF photoresist, in order to cope with miniaturization, a thin photoresist is often used compared to the case of KrF photoresist. For example, an appropriate thickness for photoresist is up to three times the line width desired to be exposed. Accordingly, when exposure is performed for a line width of 0.13 μm, a photoresist thickness becomes approximately 0.4 μm, and when exposure is performed for a line width of 0.09 μm, a photoresist thickness becomes thinner, i.e., 0.3 μm at most.
Despite such a situation, since a silicon dioxide layer and a silicon nitride layer require relatively high ion energy in etching in general, the shape of the photoresist pattern 205 is deformed by the ion energy.
Therefore, when the hard mask 204 made of silicon dioxide is etched in the step of FIG. 1B, the photoresist pattern 205 is also etched, and the thickness thereof is reduced. Thus, the shape of the photoresist pattern 205 becomes unstable. This also causes the shape of the trench mask 206, which is formed by use of the photoresist pattern 205 as an etching mask, to become unstable, and, as shown in the plan view of FIG. 2, large irregularities are formed on the edges of the trench mask 206. Accordingly, despite the use of ArF exposure suitable for miniaturization, the processing accuracies of the trenches 201a are deteriorated and, ultimately, devices cannot be miniaturized.